1. Field of the Invention
The present invention relates to a level shifter for converting a level of an inputted signal into another level to output the signal, and more particularly to a level shifter for level-converting an inputted high level signal into a low level signal.
2. Description of the Related Art
In recent years, an increasing number of microcomputers are designed to have a large number of devices such as an ASIC, a microprocessor, a memory, and a peripheral circuit mounted on a mother board of a computer to satisfy a desirable function. In particular, the ASIC and the microcomputer are designed such that an amplitude of a power source voltage used in the inside becomes smaller, because a reduction in consumption power and operation at a high frequency are required. For example, an internal power source voltage is 2.5V. This voltage is expected to decrease to 1.8 V, 1.5 V, and 1.2 V in the future.
In contrast to this, in many cases, in accordance with a JEDEC system interface standard or the like, data input and output operation between respective devices is conducted at 3.3V and a device such as the peripheral circuit is operated at 3.3 V. Therefore, occurrence of a situation in which the peripheral circuit is operated at a voltage different from operating voltages of the ASIC and the microcomputer is becoming more frequent. Thus, the ASIC and the microcomputer are provided with input and output buffers in order to adjust a voltage difference between the inside and the outside by level shifting.
With respect to a first conventional technique, as shown in FIG. 3, there has been generally known, as an input buffer, a level shifter circuit in which a plurality of inverters are connected in series for level shifting, as an input and output buffer (for example, see JP 03-125515 A).
As shown in FIG. 3, the level shifter circuit that shifts a high voltage level to a low voltage level includes a first inverter circuit and a second inverter circuit. The first inverter circuit is composed of a P-type MOS transistor MP11 and an N-type MOS transistor MN11, which have a tolerant voltage of 3.3 V and are connected between a Vdd (1.2 V) terminal and a GND terminal and. The gates of the MOS transistors MP11 and MN11 are commonly connected with an input terminal. The second inverter circuit is composed of a P-type MOS transistor MP12 and an N-type MOS transistor MN12, which have a tolerant voltage of 1.2 V and are connected between the Vdd (1.2 V) terminal and the GND terminal. The gates of the MOS transistors MP12 and MN12 are commonly connected with the drains of the P-type MOS transistor MP11 and the N-type MOS transistor MN11. The output of the level shifter circuit is taken out from the drains of the transistors composing the second inverter circuit.
According to such a structure, it is possible that an input signal having an amplitude of 3.3 V is inverted to outputted as an inverted signal having an amplitude of 1.2 V by the first inverter circuit and then the inverted signal is inverted again to be outputted as a signal which is in phase with the input signal by the second inverter circuit.
Also, with respect to a second conventional technique, as shown in FIG. 6, there is another level shifter circuit provided with a CMOS inverter INV11 and a current mirror flip-flop latch circuit composed of P-type MOS transistors MP13 and MP14 and N-type MOS transistors MN13 and MN14 (for example, see JP 11-239051 A).
However, when the level shifter circuit is composed of the two inverter circuits as described in the first conventional technique, as shown in FIGS. 4A to 4F, a duty ratio of an output signal Vout reduces with respect to an input signal Vin, as a source voltage of the P-type MOS transistor of the first inverter circuit decreases.
Hereinafter, the description of the operation of the first inverter circuit will be made in the case where a threshold voltage Vtn of the N-type MOS transistor is set to 0.5 V, a threshold voltage Vtp of the P-type MOS transistor is set to 0.5 V, an amplitude of the input signal Vin is set to 3.3 V, and Vdd is set to 1.2 V.
Referring to FIG. 5, description will be made with respect to input and output voltage waveforms of the first inverter circuit. In the case where the input signal Vin increases from 0 V to 3.3 V, because the threshold voltage of the N-type MOS transistor is 0.5 V, the N-type MOS transistor MN11 is turned on at a time when Vin reaches 0.5 V. Then, an output signal Vmid of the first inverter circuit decreases from 1.2 V to 0 V. In contract to this, in the case where Vin decreases from 3.3 V to 0 V, the P-type MOS transistor MP11 is turned on at a time when Vin reaches 0.7 V (note that, because the threshold voltage of the P-type MOS transistor is 0.5 V and the source thereof is connected with the terminal (Vdd=1.2 V), 1.2 V−0.5 V=0.7 V is obtained). Then, the output signal Vmid of the first inverter circuit increases from 0 V to 1.2 V. Because only Vdd (=1.2 V) is applied to the source of the P-type MOS transistor, a time period T1 from the time at which Vin rises from 0 V to the time at which the N-type MOS transistor turns on is different from a time period T2 from the time at which Vin falls from 3.3V to the time at which the P-type MOS transistor turns on. Thus, a problem is caused in that a duty ratio of the output signal Vmid is different from a duty ratio of the input signal Vin in the first inverter circuit.
With respect to the second conventional technique, when Vin falls from 3.3 V, Vin is inverted by the inverter INV11 and transferred to the N-type MOS transistor MN14 to thereby turn on the N-type MOS transistor MN14, which causes a voltage of an output signal Vout to become 0 V. On the other hand, when Vin rises from 0 V, the N-type MOS transistor MN13 is turned on, so that a charge is pulled from the gate of the P-type MOS transistor MP14, which causes the voltage of the output signal Vout to become 1.2 V. As described above, the output signal Vout is determined when a gate electrode of any one of the N-type MOS transistors MN13 and MN14 becomes 3.3 V. When the output signal Vout becomes 0 V, only the N-type MOS transistor MN14 is turned on, that is, the output is changed by one stage gate. In contrast to this, when the output signal Vout becomes 1.2 V, the N-type MOS transistor MN13 is turned on and then the P-type MOS transistor MP14 is turned on. That is, the output is changed by two stage gates. Accordingly, timing of the output in the case where the output signal Vout rises is different from timing of the output in the case where the output signal Vout falls. Thus, as in the case of the first conventional technique, a problem is caused in that a duty ratio of the output signal Vout is different from a duty ratio of the input signal. Note that, because the inverter INV11 operates at an amplitude of 3.3 V, no substantial delay is caused.
The problems with respect to the first and second conventional techniques become remarkable as a frequency of the input signal becomes higher and as an amplitude difference between the input signal and the output signal increases.